Movellus provides Intelligent Clock Network IP for optimizing clock distribution for SOCs. The Movellus IP overcomes the challenges associated with traditional clock trees and clock meshes, resulting in better PPA.
By using Movellus’ IP chip designers created silicon with 38% greater performance or 10–30% lower energy consumption. When you combine these gains with process-node advancements, and the potential result can be more than 50% performance gains.
Across the clock-design and closure stages, the Movellus Maestro IP architecture provides enhancements over existing architectures and creates new opportunities for greater clock synchronization across silicon. It improves chip-level performance and power.
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